1. Field of the Invention
The present invention relates to a display driving circuit, and more particularly, to a display driving circuit which exhibits excellent output characteristics due to improved performance and has excellent reliability.
2. Discussion of Related Art
In general, it is difficult to diversely integrate circuits for driving pixels in a liquid crystal display (LCD) panel employing amorphous silicon (a-Si) thin-film transistors (TFTs) due to low mobility, unlike an LCD panel employing low-temperature polysilicon TFTs.
To solve this problem, active attempts to integrate regions capable of operating at a low frequency in a panel have been made lately. Among the attempts, integrating a gate driver circuit in a panel is considered the most efficient technique, and also the resultant product has been put on the market. Multiple LCD driving circuits in which a gate driver circuit is integrated according to conventional art are disclosed in Korean Patent Registration No. 705628 filed by the present Applicant, and so on.
To overcome low mobility, a gate driver circuit integrated in an LCD panel increases the width of a TFT and forms a shift register circuit using a bootstrap effect.
FIG. 1 is a block diagram of a shift register circuit using a general bootstrap effect. A shift register circuit using a bootstrap effect may use 2-phase driving or 4-phase driving. In 2-phase driving, a clock signal used for synchronization of a shift register operation and current supply is synchronized with one horizontal time, which corresponds to the high-level section of a gate pulse, and two clock signals having a phase difference of 180° are used. In 4-phase driving, a clock signal used for synchronization of a shift register operation and current supply is synchronized with one horizontal time, like 2-phase driving, but four clock signals having a phase difference of 90° are used, that is, a clock signal whose high-level section is repeated every four horizontal times is used.
FIG. 2(A) shows waveforms of a shift register using 2-phase driving, and FIG. 2(B) shows waveforms of a shift register using 4-phase driving.
Referring to FIGS. 1 and 2, a previous-stage output (generally an (N−1)th or (N−2)th output) is input through an input portion 11, and then a TFT of the input portion 11 is switched to its off-state, so that a bootstrap node P-node becomes a floating node. Subsequently, when a clock signal is raised from a low-level voltage VGL to a high-level voltage VGH during a horizontal time, the bootstrap node P-node in the floating state is ideally raised to about double the high-level voltage VGH (generally 2 VGH−a) due to the coupling effect of the clock signal.
At this time, since the voltage raised by the bootstrap effect is applied to the gate node of an output TFT T11, large current can flow through the output TFT T11, and the clock signal is output to an output node without significant loss of a rise/fall delay time. A signal delay of one horizontal time occurs between the input signal and the output signal, and thus the shift register circuit can normally operate.
Next, Korean Patent Registration No. 705628 filed by the present Applicant will be described as an example of a driving circuit in which a gate driver circuit is embedded according to conventional art. FIG. 3 is a circuit diagram of an LCD driving circuit disclosed in Korean Patent Registration No. 705628.
Referring to FIG. 3, a conventional driving circuit includes eight TFTs T1 to T8, and two capacitors C1 and C2. The driving circuit of FIG. 3 includes a pull-up/pull-down circuit portion 130 having a pull-up portion T3 generating a gate high-level voltage, and pull-down portions T2 and T4 generating a gate low-level voltage. To implement a pull-down function, an output of n-type TFT (NTFT) inverter circuits T5 and T6 is used as a control signal.
An output signal X of the inverter circuits T5 and T6 is applied to the TFT gate nodes of the pull-down portions T2 and T4. At this time, an increase in gate voltage leads to improvement in circuit performance, but deteriorates the TFTs due to stress caused by gate node bias voltage, which results in deterioration of reliability. In general, when the TFTs of pull-down portions T2 and T4 are turned off, a gate-source voltage (Vgs) of the TFTs is frequently 0 V or more, and in this case, there is leakage current.
FIG. 4 shows graphs illustrating leakage current increasing when mobility increases or a threshold voltage Vth decreases according to current-voltage (I-V) characteristics of a TFT. As shown in FIG. 4, when the Vgs of a TFT is 0 V or more, an increase in mobility or a reduction in the threshold voltage Vth leads to an increase in leakage current according to I-V characteristics of the TFT, thereby deteriorating circuit performance.
Further, when the threshold voltage Vth is low and a mobility increasing factor, such as high temperature, occurs in the high-level section of an output of a gate driver integrated as a circuit leakage current component in the circuit of the pull-down portions T2 and T4, the output of the gate driver is attenuated and output.